On Sun, Mar 04, 2012 at 02:26:13PM +0000, Blue Swirl wrote: > > It seems to have to do with the host bridge. > > It's unusual to have host bridge present itself > > as a pci to pci bridge but there it is. > > It looks like the I/O base calculations in OpenBIOS are confused
Where's the source for that, BTW? Have build instructions? > by > host bridge, after that all BARs are wrong. OpenBIOS also thinks that > the host bridge is a device and attempts to configure six BARs instead > of two. According to the spec it is a device, so should be ok? If I just make BAR4 writeable we get past the bios screen at least. Maybe openbios gets confused if a device has no BARs? Do things work for you with the patch below? All it does is make BAR4 writeable, accesses go nowhere. diff --git a/hw/apb_pci.c b/hw/apb_pci.c index 1d25da8..fae841f 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -433,6 +433,7 @@ static int pbm_pci_host_init(PCIDevice *d) pci_set_word(d->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); + pci_set_long(d->wmask + 0x20, 0xfffffff0); return 0; } @@ -444,7 +445,6 @@ static void pbm_pci_host_class_init(ObjectClass *klass, void *data) k->vendor_id = PCI_VENDOR_ID_SUN; k->device_id = PCI_DEVICE_ID_SUN_SABRE; k->class_id = PCI_CLASS_BRIDGE_HOST; - k->is_bridge = 1; } static TypeInfo pbm_pci_host_info = { -- MST