On Wed, Oct 25, 2023 at 10:50:00AM -0300, Daniel Henrique Barboza wrote: > RVG behaves like a profile: a single flag enables a set of bits. Right > now we're considering user choice when handling RVG and zicsr/zifencei > and ignoring user choice on MISA bits. > > We'll add user warnings for profiles when the user disables its > mandatory extensions in the next patch. We'll do the same thing with RVG > now to keep consistency between RVG and profile handling. > > First and foremost, create a new RVG only helper to avoid clogging > riscv_cpu_validate_set_extensions(). We do not want to annoy users with > RVG warnings like we did in the past (see 9b9741c38f), thus we'll only > warn if RVG was user set and the user disabled a RVG extension in the > command line. > > For every RVG MISA bit (IMAFD), zicsr and zifencei, the logic then > becomes: > > - if enabled, do nothing; > - if disabled and not user set, enable it; > - if disabled and user set, throw a warning that it's a RVG mandatory > extension. > > This same logic will be used for profiles in the next patch. > > Note that this is a behavior change, where we would error out if the > user disabled either zicsr or zifencei. As long as users are explicitly > disabling things in the command line we'll let them have a go at it, at > least in this step. We'll error out later in the validation if needed. > > Other notable changes from the previous RVG code: > > - use riscv_cpu_write_misa_bit() instead of manually updating both > env->misa_ext and env->misa_ext_mask; > > - set zicsr and zifencei directly. We're already checking if they > were user set and priv version will never fail for these > extensions, making cpu_cfg_ext_auto_update() redundant. > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > --- > target/riscv/tcg/tcg-cpu.c | 73 +++++++++++++++++++++++++------------- > 1 file changed, 48 insertions(+), 25 deletions(-) >
Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>