Fixes: 40336d5b1d4c "target/riscv: Add HS-mode virtual interrupt and IRQ
filtering support."
Cc: Rajnesh Kanwal <rkan...@rivosinc.com>
Cc: Alistair Francis <alistair.fran...@wdc.com>
Signed-off-by: Michael Tokarev <m...@tls.msk.ru>
---
target/riscv/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bf58b0f0b5..d74b361be6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -214,13 +214,13 @@ struct CPUArchState {
/*
* When mideleg[i]=0 and mvien[i]=1, sie[i] is no more
- * alias of mie[i] and needs to be maintained separatly.
+ * alias of mie[i] and needs to be maintained separately.
*/
uint64_t sie;
/*
* When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more
- * alias of sie[i] (mie[i]) and needs to be maintained separatly.
+ * alias of sie[i] (mie[i]) and needs to be maintained separately.
*/
uint64_t vsie;
--
2.39.2
