The following changes since commit 8fa379170c2a12476021f5f50d6cf3f672e79e7b:
Update version for v8.2.0-rc1 release (2023-11-21 13:56:12 -0500) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231122 for you to fetch changes up to 6bca4d7d1ff2b8857486c3ff31f5c6fc3e3984b4: target/riscv/cpu_helper.c: Fix mxr bit behavior (2023-11-22 14:03:37 +1000) ---------------------------------------------------------------- Fourth RISC-V PR for 8.2 This is a few bug fixes for the 8.2 release * Add Zicboz block size to hwprobe * Creat the virt machine FDT before machine init is complete * Don't verify ISA compatibility for zicntr and zihpm * Fix SiFive E CLINT clock frequency * Fix invalid exception on MMU translation stage * Fix mxr bit behavior ---------------------------------------------------------------- Clément Chigot (1): target/riscv: don't verify ISA compatibility for zicntr and zihpm Daniel Henrique Barboza (1): hw/riscv/virt.c: do create_fdt() earlier, add finalize_fdt() Ivan Klokov (2): target/riscv/cpu_helper.c: Invalid exception on MMU translation stage target/riscv/cpu_helper.c: Fix mxr bit behavior Palmer Dabbelt (1): linux-user/riscv: Add Zicboz block size to hwprobe Román Cárdenas (1): riscv: Fix SiFive E CLINT clock frequency hw/riscv/sifive_e.c | 2 +- hw/riscv/virt.c | 71 +++++++++++++++++++++++++++------------------- linux-user/syscall.c | 6 ++++ target/riscv/cpu_helper.c | 54 +++++++++++++++++------------------ target/riscv/tcg/tcg-cpu.c | 9 ++++++ 5 files changed, 85 insertions(+), 57 deletions(-)
