On 11/23/23 11:30, Nicholas Piggin wrote:
The chiptod/TFMR/state machine is not really tied to the other
time register fixes, but they touch some of the same code, and
logically same facility.
Changes since v1 of chiptod patches:
- Split hackish ChipTOD<->TFMR/TBST interface into its own patch
- Fix multi-socket addressing on P9 / chip ID mode (P10 works)
- Change chiptod primary/secondary setting to use class properties
- Add more comments to explain TOD overview and timebase state
machine.
- SMT support for TFMR, some functionality is limited to thread 0.
- FIRMWARE_CONTROL_ERROR bit implemented in TFMR.
- Misc cleanups and bug fixes.
The hacky part, addressing core from chiptod, is still hacky. Is
there strong objection to it?
Dunno yet :)
This successfully runs skiboot chiptod initialisation code with
POWER9 and POWER10 multi-socket, multi-core, SMT. That requires
skiboot 7.1 (not in-tree), otherwise chiptod init is skipped on
QEMU machines.
Let's update skiboot at the same time then.
Thanks,
C.
Thanks,
Nick
Nicholas Piggin (7):
target/ppc: Rename TBL to TB on 64-bit
target/ppc: Improve timebase register defines naming
target/ppc: Fix move-to timebase SPR access permissions
pnv/chiptod: Add POWER9/10 chiptod model
pnv/chiptod: Implement the ChipTOD to Core transfer
target/ppc: Implement core timebase state machine and TFMR
target/ppc: Add SMT support to time facilities
include/hw/ppc/pnv_chip.h | 3 +
include/hw/ppc/pnv_chiptod.h | 55 ++++
include/hw/ppc/pnv_core.h | 4 +
include/hw/ppc/pnv_xscom.h | 9 +
target/ppc/cpu.h | 50 +++-
hw/ppc/pnv.c | 63 +++++
hw/ppc/pnv_chiptod.c | 509 +++++++++++++++++++++++++++++++++++
target/ppc/helper_regs.c | 39 ++-
target/ppc/ppc-qmp-cmds.c | 4 +
target/ppc/timebase_helper.c | 309 ++++++++++++++++++++-
target/ppc/translate.c | 42 ++-
hw/ppc/meson.build | 1 +
hw/ppc/trace-events | 4 +
13 files changed, 1067 insertions(+), 25 deletions(-)
create mode 100644 include/hw/ppc/pnv_chiptod.h
create mode 100644 hw/ppc/pnv_chiptod.c