On Tue, 28 Nov 2023, Philippe Mathieu-Daudé wrote:
On 28/11/23 13:47, BALATON Zoltan wrote:
On Sun, 26 Nov 2023, BALATON Zoltan wrote:
Philippe,
Could this be merged for 8.2 as it fixes USB on the amigaone machine?
This would be useful as usb-storage is the simplest way to share data
with the host with these machines.
Philippe, do you have some time to look at this now for 8.2 please? I still
hope this could be fixed for the amigaone machine on release and dont' have
to wait until the next one for USB to work on that machine.
Thanks for your detailed cover and patch descriptions.
I just finished to run my tests and they all passed.
I couldn't spend much time reviewing the patches, but having a quick
look I don't think the way you model it is correct. This is a tricky
setup and apparently we don't fully understand it (I understand what
you explained, but some pieces don't make sense to me). That said,
I understand it help you and the AmigaOne users, and nobody objected.
So, while being a bit reluctant, I am queuing this series; and will
send a PR in a few. We'll have time to improve this model later.
Thanks very much. I'm open to further discussion and improving this model,
just wanted to have something working in master now. The discussion about
this seemed never ending, it started before 8.0 and still could not get to
a conclusion yet so until then this should work for now and allow users to
use it and does not prevent improving it later. So I'm still interested in
your review and why do you think this is not modelling it correctly but we
have more time for that now and can change this further as a follow up.
I think the current way makes it easier to add Bernhard's SCI interrupt as
well for which I had a review proposal before. The main disagreement
seemsd to be if the chip functions should be PCI devices or not. I think
they aren't like regular PCI devices and clearly don't use PCI interrupts
so Mark's and Bernhard's idea to use PCI bus interrupt routing for these
does not work because they need to be independently routable to ISA
interrupts. So whatever we do we'll need to distinguish the interrupt
sources and keep track of their state individually because more than one
of them can control a single ISA IRQ. Doing this in the ISA bridge seems
like the best place because that already owns the ISA interrupts so no
other component will need access to them and it can keep track of state of
IRQ sources at one place.
Regards,
BALATON Zoltan
