On 11/30/23 11:19, Max Filippov wrote:
Don't embed ibreak exception generation into TB and don't invalidate TB
on ibreak address change. Add CPUBreakpoint pointers to xtensa
CPUArchState, use cpu_breakpoint_insert/cpu_breakpoint_remove_by_ref to
manage ibreak breakpoints and provide TCGCPUOps::debug_check_breakpoint
callback that recognizes valid instruction breakpoints.
Signed-off-by: Max Filippov <jcmvb...@gmail.com>
---
target/xtensa/cpu.c | 1 +
target/xtensa/cpu.h | 4 ++++
target/xtensa/dbg_helper.c | 46 +++++++++++++++++++++++++-------------
target/xtensa/helper.c | 12 ++++++++++
target/xtensa/translate.c | 17 --------------
5 files changed, 47 insertions(+), 33 deletions(-)
Thanks a bunch,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
