Hi, Drew brought to my attention the following post on the tech-unprivileged mailing list:
"Architecture Review Committee meeting minutes, 12/19/23" https://lists.riscv.org/g/tech-unprivileged/message/611 Second paragraph mentions: "In response to some recent discussion in the Apps and Tools HC about how profiles should be represented in GCC/LLVM, the ARC provides this answer: compilers should use a single parameter for an ISA string. An ISA string begins with either a base ISA name (e.g. rv64i) or a profile name (e.g. rva23u64) and is optionally followed by additional extensions (e.g. rv64imac_zicond or rva23u64_zfh_zicond). If the ISA string begins with a profile name, it is equivalent to replacing the profile name with its mandatory base ISA and its mandatory extensions; any optional extensions in a profile must be explicitly named if their inclusion is desired. ISAs are sets, and concatenating strings takes the union, so redundancy is legal (e.g. rva23u64, rva23u64_zicsr, and rva23u64_zicsr_zicsr are all valid and equivalent)." The takeaways from it: - this implementation is compliant with how profiles are interpreted, i.e. a profile is considered a set of the mandatory base ISA and mandatory extensions, and any additional/optional extensions must be explicitly named; - our ISA string format is also since we use the base ISA name + extensions format already. This series don't change/add anything in this regard. If we have enough demand for it, I can do a follow-up to add support for the ISA string profile format. I.e. this: $ build/qemu-system-riscv64 -M virt -cpu rva22s64 (...) # cat /proc/device-tree/cpus/cpu@0/riscv,isa rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt Would become this: # cat /proc/device-tree/cpus/cpu@0/riscv,isa rva22s64 Feel free to comment here if you, as a toolchain/application developer, thinks that this ISA string profile format makes it easier to deal with profiles or if you're fine with just parsing all the extensions in the current ISA string format. All of this relies on this series being upstreamed first, of course. Alistair, let me know if we're missing anything. Thanks, Daniel On 12/18/23 09:53, Daniel Henrique Barboza wrote:
Hi, This is a merge of the two profile series: "[PATCH for-9.0 v12 00/18] riscv: rv64i/rva22u64 CPUs, RVA22U64 profile support" "[PATCH for-9.0 v2 0/8] target/riscv: implement RVA22S64 profile" I'm sending them together since the second series is dependent on the first. Quick summary of the major features added: - A new rv64i CPU type. This is a CPU that has only RVI enabled; - 'rva22u64' and 'rva22s64' profile flags. They were designed to be used with the 'rv64i' CPU but can be used with other generic CPUs like rv64; - Two new profile CPUs: 'rva22u64' and 'rva22s64'. A profile CPU is an alias of '-cpu rv64,profile=on' and it's the most convenient way of using profiles. E.g to launch an rva22s64 'virt' machine: ./qemu-system-riscv64 -M virt -cpu rva22s64 (...) To test an application with an rva22u64 profile with linux-user mode: ./qemu-riscv64 -cpu rva22u64 (...) The series can also be fetch via: https://gitlab.com/danielhb/qemu/-/tree/rva22_v13 Patches rebased on top of Alistair riscv-to-apply.next. All patches acked. Daniel Henrique Barboza (26): target/riscv: create TYPE_RISCV_VENDOR_CPU target/riscv/tcg: do not use "!generic" CPU checks target/riscv/tcg: update priv_ver on user_set extensions target/riscv: add rv64i CPU target/riscv: add zicbop extension flag target/riscv/tcg: add 'zic64b' support riscv-qmp-cmds.c: expose named features in cpu_model_expansion target/riscv: add rva22u64 profile definition target/riscv/kvm: add 'rva22u64' flag as unavailable target/riscv/tcg: add user flag for profile support target/riscv/tcg: add MISA user options hash target/riscv/tcg: add riscv_cpu_write_misa_bit() target/riscv/tcg: handle profile MISA bits target/riscv/tcg: add hash table insert helpers target/riscv/tcg: honor user choice for G MISA bits target/riscv/tcg: validate profiles during finalize riscv-qmp-cmds.c: add profile flags in cpu-model-expansion target/riscv: add 'rva22u64' CPU target/riscv: implement svade target/riscv: add priv ver restriction to profiles target/riscv/cpu.c: finalize satp_mode earlier target/riscv/cpu.c: add riscv_cpu_is_32bit() target/riscv: add satp_mode profile support target/riscv: add 'parent' in profile description target/riscv: add RVA22S64 profile target/riscv: add rva22s64 cpu hw/riscv/virt.c | 5 + target/riscv/cpu-qom.h | 5 + target/riscv/cpu.c | 201 +++++++++++++-- target/riscv/cpu.h | 18 ++ target/riscv/cpu_cfg.h | 4 + target/riscv/kvm/kvm-cpu.c | 7 +- target/riscv/riscv-qmp-cmds.c | 44 +++- target/riscv/tcg/tcg-cpu.c | 450 +++++++++++++++++++++++++++++++--- 8 files changed, 672 insertions(+), 62 deletions(-)