On Fri, Dec 29, 2023 at 12:08 PM Atish Patra <ati...@rivosinc.com> wrote: > > From: Kaiwen Xue <kaiw...@rivosinc.com> > > This adds the definitions for ISA extension smcntrpmf. > > Signed-off-by: Kaiwen Xue <kaiw...@rivosinc.com> > Signed-off-by: Atish Patra <ati...@rivosinc.com> > --- > target/riscv/cpu.c | 1 - > target/riscv/cpu.h | 6 ++++++ > target/riscv/cpu_bits.h | 29 +++++++++++++++++++++++++++++ > 3 files changed, 35 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index da3f05cd5373..54395f95b299 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1297,7 +1297,6 @@ const char *riscv_get_misa_ext_description(uint32_t bit) > const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > - DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false),
Can you explain why you are removing this in the commit message? Alistair > MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), > MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d74b361be641..34617c4c4bab 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -319,6 +319,12 @@ struct CPUArchState { > > target_ulong mcountinhibit; > > + /* PMU cycle & instret privilege mode filtering */ > + target_ulong mcyclecfg; > + target_ulong mcyclecfgh; > + target_ulong minstretcfg; > + target_ulong minstretcfgh; > + > /* PMU counter state */ > PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index ebd7917d490a..0ee91e502e8f 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -401,6 +401,10 @@ > /* Machine counter-inhibit register */ > #define CSR_MCOUNTINHIBIT 0x320 > > +/* Machine counter configuration registers */ > +#define CSR_MCYCLECFG 0x321 > +#define CSR_MINSTRETCFG 0x322 > + > #define CSR_MHPMEVENT3 0x323 > #define CSR_MHPMEVENT4 0x324 > #define CSR_MHPMEVENT5 0x325 > @@ -431,6 +435,9 @@ > #define CSR_MHPMEVENT30 0x33e > #define CSR_MHPMEVENT31 0x33f > > +#define CSR_MCYCLECFGH 0x721 > +#define CSR_MINSTRETCFGH 0x722 > + > #define CSR_MHPMEVENT3H 0x723 > #define CSR_MHPMEVENT4H 0x724 > #define CSR_MHPMEVENT5H 0x725 > @@ -885,6 +892,28 @@ typedef enum RISCVException { > /* PMU related bits */ > #define MIE_LCOFIE (1 << IRQ_PMU_OVF) > > +#define MCYCLECFG_BIT_MINH BIT_ULL(62) > +#define MCYCLECFGH_BIT_MINH BIT(30) > +#define MCYCLECFG_BIT_SINH BIT_ULL(61) > +#define MCYCLECFGH_BIT_SINH BIT(29) > +#define MCYCLECFG_BIT_UINH BIT_ULL(60) > +#define MCYCLECFGH_BIT_UINH BIT(28) > +#define MCYCLECFG_BIT_VSINH BIT_ULL(59) > +#define MCYCLECFGH_BIT_VSINH BIT(27) > +#define MCYCLECFG_BIT_VUINH BIT_ULL(58) > +#define MCYCLECFGH_BIT_VUINH BIT(26) > + > +#define MINSTRETCFG_BIT_MINH BIT_ULL(62) > +#define MINSTRETCFGH_BIT_MINH BIT(30) > +#define MINSTRETCFG_BIT_SINH BIT_ULL(61) > +#define MINSTRETCFGH_BIT_SINH BIT(29) > +#define MINSTRETCFG_BIT_UINH BIT_ULL(60) > +#define MINSTRETCFGH_BIT_UINH BIT(28) > +#define MINSTRETCFG_BIT_VSINH BIT_ULL(59) > +#define MINSTRETCFGH_BIT_VSINH BIT(27) > +#define MINSTRETCFG_BIT_VUINH BIT_ULL(58) > +#define MINSTRETCFGH_BIT_VUINH BIT(26) > + > #define MHPMEVENT_BIT_OF BIT_ULL(63) > #define MHPMEVENTH_BIT_OF BIT(31) > #define MHPMEVENT_BIT_MINH BIT_ULL(62) > -- > 2.34.1 > >