On Tue, Dec 12, 2023 at 9:04 PM Irina Ryapolova <irina.ryapol...@syntacore.com> wrote: > > [Changes since v1] > used satp_mode.map instead of satp_mode.supported
The changelog needs to go > > [Original cover] > The SATP register is an SXLEN-bit read/write WARL register. It means that CSR > fields are only defined > for a subset of bit encodings, but allow any value to be written while > guaranteeing to return a legal > value whenever read (See riscv-privileged-20211203, SATP CSR). > > For example on rv64 we are trying to write to SATP CSR val = > 0x1000000000000000 (SATP_MODE = 1 - Reserved for standard use) > and after that we are trying to read SATP_CSR. We read from the SATP CSR > value = 0x1000000000000000, which is not a correct > operation (return illegal value). > > Signed-off-by: Irina Ryapolova <irina.ryapol...@syntacore.com> > --- Below this line. Otherwise it will be included in the git history, which we don't want Alistair > target/riscv/csr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index fde7ce1a53..735fb27be7 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1278,8 +1278,8 @@ static RISCVException read_mstatus(CPURISCVState *env, > int csrno, > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > - return (vm & 0xf) <= > - satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map); > + uint64_t mode_supported = riscv_cpu_cfg(env)->satp_mode.map; > + return get_field(mode_supported, (1 << vm)); > } > > static target_ulong legalize_mpp(CPURISCVState *env, target_ulong old_mpp, > -- > 2.25.1 > >