> On Jan 10, 2024, at 8:01 AM, Philippe Mathieu-Daudé <phi...@linaro.org> wrote: > > IIUC Goldfish virtual HW is maintained externally by Google > https://android.googlesource.com/platform/external/qemu/+/master/docs/GOLDFISH-VIRTUAL-HARDWARE.TXT > > I suppose the spec needs to be updated before the change can be > accepted in mainstream QEMU, but since I'm not sure I Cc'ed Alex, > David and Laurent.
Hey Philippe, I have seen that document didn’t realize that it was the source of truth for the Goldfish devices in Qemu, as Qemu already has Goldfish devices that deviate in behavior from that document. In particular: 1. There is no distinction between “rtc” and “timer” in Qemu. 2. The Goldfish “pic” device does not behave as that document describes. In particular, the “NUMBER” register is described in that document as returning the lowest pending interrupt index or 0 for none (i.e. a number in the range 0..32). But Qemu returns a bitmask of pending interrupts when that register is read. And despite the name “DISABLE_ALL” that document claims that writing to it merely clears the pending interrupts without disabling them (which would be quite the trick with level-triggered interrupt sources) whereas in Qemu, it does both clear and disable. (I am not, in any way, advocating for a behavior change in Qemu, BTW… I just thought that referenced docuemnt was no longer relevant.) -- thorpej
