On 1/15/24 11:13, Zhenzhong Duan wrote:
> This is a prerequisite for host cap/ecap sync.
>
> No functional change intended.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
Looks good to me
Reviewed-by: Eric Auger <eric.au...@redhat.com>
Eric
> ---
> hw/i386/intel_iommu.c | 92 +++++++++++++++++++++++--------------------
> 1 file changed, 50 insertions(+), 42 deletions(-)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 95faf697eb..4c1d058ebd 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -4009,30 +4009,10 @@ static void vtd_iommu_replay(IOMMUMemoryRegion
> *iommu_mr, IOMMUNotifier *n)
> return;
> }
>
> -/* Do the initialization. It will also be called when reset, so pay
> - * attention when adding new initialization stuff.
> - */
> -static void vtd_init(IntelIOMMUState *s)
> +static void vtd_cap_init(IntelIOMMUState *s)
> {
> X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
>
> - memset(s->csr, 0, DMAR_REG_SIZE);
> - memset(s->wmask, 0, DMAR_REG_SIZE);
> - memset(s->w1cmask, 0, DMAR_REG_SIZE);
> - memset(s->womask, 0, DMAR_REG_SIZE);
> -
> - s->root = 0;
> - s->root_scalable = false;
> - s->dmar_enabled = false;
> - s->intr_enabled = false;
> - s->iq_head = 0;
> - s->iq_tail = 0;
> - s->iq = 0;
> - s->iq_size = 0;
> - s->qi_enabled = false;
> - s->iq_last_desc_type = VTD_INV_DESC_NONE;
> - s->iq_dw = false;
> - s->next_frcd_reg = 0;
> s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
> VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
> VTD_CAP_MGAW(s->aw_bits);
> @@ -4049,27 +4029,6 @@ static void vtd_init(IntelIOMMUState *s)
> }
> s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
>
> - /*
> - * Rsvd field masks for spte
> - */
> - vtd_spte_rsvd[0] = ~0ULL;
> - vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
> - x86_iommu->dt_supported);
> - vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
> - vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
> - vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
> -
> - vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
> -
> x86_iommu->dt_supported);
> - vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
> -
> x86_iommu->dt_supported);
> -
> - if (s->scalable_mode || s->snoop_control) {
> - vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
> - vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
> - vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
> - }
> -
> if (x86_iommu_ir_supported(x86_iommu)) {
> s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
> if (s->intr_eim == ON_OFF_AUTO_ON) {
> @@ -4102,7 +4061,56 @@ static void vtd_init(IntelIOMMUState *s)
> if (s->pasid) {
> s->ecap |= VTD_ECAP_PASID;
> }
> +}
> +
> +/*
> + * Do the initialization. It will also be called when reset, so pay
> + * attention when adding new initialization stuff.
> + */
> +static void vtd_init(IntelIOMMUState *s)
> +{
> + X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
> +
> + memset(s->csr, 0, DMAR_REG_SIZE);
> + memset(s->wmask, 0, DMAR_REG_SIZE);
> + memset(s->w1cmask, 0, DMAR_REG_SIZE);
> + memset(s->womask, 0, DMAR_REG_SIZE);
> +
> + s->root = 0;
> + s->root_scalable = false;
> + s->dmar_enabled = false;
> + s->intr_enabled = false;
> + s->iq_head = 0;
> + s->iq_tail = 0;
> + s->iq = 0;
> + s->iq_size = 0;
> + s->qi_enabled = false;
> + s->iq_last_desc_type = VTD_INV_DESC_NONE;
> + s->iq_dw = false;
> + s->next_frcd_reg = 0;
> +
> + /*
> + * Rsvd field masks for spte
> + */
> + vtd_spte_rsvd[0] = ~0ULL;
> + vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> + vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
> + vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
> +
> + vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> + vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
> + x86_iommu->dt_supported);
> +
> + if (s->scalable_mode || s->snoop_control) {
> + vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
> + vtd_spte_rsvd_large[2] &= ~VTD_SPTE_SNP;
> + vtd_spte_rsvd_large[3] &= ~VTD_SPTE_SNP;
> + }
>
> + vtd_cap_init(s);
> vtd_reset_caches(s);
>
> /* Define registers with default values and bit semantics */
