On Wed, Jan 24, 2024 at 12:55:49PM +0000, Conor Dooley wrote: > From: Conor Dooley <conor.doo...@microchip.com> > > A cpu may not have the same xlen as the compile time target, and > misa_mxl_max is the source of truth for what the hart supports. > > The conversion from misa_mxl_max to xlen already has one user, so > introduce a helper and use that to populate the isa string. > > Link: > https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/ > Signed-off-by: Conor Dooley <conor.doo...@microchip.com> > --- > I dropped the tags since I added the helper > --- > target/riscv/cpu.c | 9 ++++++++- > target/riscv/cpu.h | 1 + > target/riscv/gdbstub.c | 2 +- > 3 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ad1df2318b..4aa4b2e988 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -307,6 +307,11 @@ void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL > mxl, uint32_t ext) > env->misa_ext_mask = env->misa_ext = ext; > } > > +int riscv_cpu_max_xlen(CPURISCVState env) > +{ > + return 16 << env.misa_mxl_max; > +}
Something like this could probably be a static inline in the header. > + > #ifndef CONFIG_USER_ONLY > static uint8_t satp_mode_from_str(const char *satp_mode_str) > { > @@ -2332,7 +2337,9 @@ char *riscv_isa_string(RISCVCPU *cpu) > int i; > const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); > char *isa_str = g_new(char, maxlen); > - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > + int xlen = riscv_cpu_max_xlen(cpu->env); > + char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", xlen); > + > for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { > if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { > *p++ = qemu_tolower(riscv_single_letter_exts[i]); > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 05e83c4ac9..aacc031397 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -511,6 +511,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int > size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr); > char *riscv_isa_string(RISCVCPU *cpu); > +int riscv_cpu_max_xlen(CPURISCVState env); > bool riscv_cpu_option_set(const char *optname); > > #define cpu_mmu_index riscv_cpu_mmu_index > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index 58b3ace0fe..f15980fdcf 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -218,7 +218,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int > base_reg) > CPURISCVState *env = &cpu->env; > GString *s = g_string_new(NULL); > riscv_csr_predicate_fn predicate; > - int bitsize = 16 << env->misa_mxl_max; > + int bitsize = riscv_cpu_max_xlen(*env); > int i; > > #if !defined(CONFIG_USER_ONLY) > -- > 2.43.0 > Otherwise, Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>