On 5/2/24 11:46, Cédric Le Goater wrote:
Hello Jamin,
On 2/5/24 10:14, Jamin Lin wrote:
According to the design of ASPEED SOCS, the uart controller
is 1 base for ast10x0, ast2600, ast2500 and ast2400.
However, the uart controller is 0 base for ast2700.
To support uart controller both 0 and 1 base,
adds uasrt_bases parameter in AspeedSoCClass
and set the default uart controller 1 base
for ast10x0, astt2600, ast2500 and ast2400.
The board definition can set 'amc->uart_default' to choose a different
default serial port for the console, or use the "bmc-console" machine
option . Isn't it enough ? May be I am misunderstanding the need.
To clarify,
ASPEED_DEV_UART1 is in the first serial port on the boards.
I think we chose to start the indexing at 1 because the Aspeed QEMU
modeling began first with the UART model (console) and for simplicity,
we copied the definitions of the device tree from Linux :
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &vuart;
We replicated this indexing starting at 1 to nearly all device models :
ASPEED_DEV_UART1 - 13
ASPEED_DEV_SPI1 -2
ASPEED_DEV_EHCI1 -2
ASPEED_DEV_TIMER1 - 8
ASPEED_DEV_ETH1 -4
ASPEED_DEV_MII1 - 4
ASPEED_DEV_JTAG0 - 1 <--- !!
ASPEED_DEV_FSI1 - 2
I don't know what would be ASPEED_DEV_UART0 in this context.
May be you could send a simplified AST2700 SoC model with definitions
of a minimum address space and IRQ space ?
Looking at TF-A definitions,
https://github.com/ARM-software/arm-trusted-firmware/commit/85f199b77447
#define UART_BASE U(0x14c33000)
#define UART12_BASE (UART_BASE + 0xb00)
#define CONSOLE_UART_BASE UART12_BASE
As Cédric described, we have TF-A UART12_BASE -> QEMU ASPEED_DEV_UART13.
