On 2/7/24 06:48, Alexander Monakov wrote:
The SSE4.1 variant is virtually identical to the SSE2 variant, except
for using 'PTEST+JNZ' in place of 'PCMPEQB+PMOVMSKB+CMP+JNE' for testing
if an SSE register is all zeroes. The PTEST instruction decodes to two
uops, so it can be handled only by the complex decoder, and since
CMP+JNE are macro-fused, both sequences decode to three uops. The uops
comprising the PTEST instruction dispatch to p0 and p5 on Intel CPUs, so
PCMPEQB+PMOVMSKB is comparatively more flexible from dispatch
standpoint.
Hence, the use of PTEST brings no benefit from throughput standpoint.
Its latency is not important, since it feeds only a conditional jump,
which terminates the dependency chain.
I never observed PTEST variants to be faster on real hardware.
Signed-off-by: Alexander Monakov<amona...@ispras.ru>
Signed-off-by: Mikhail Romanov<mmroma...@ispras.ru>
---
util/bufferiszero.c | 29 -----------------------------
1 file changed, 29 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
