On Tue, Feb 13, 2024 at 3:13 AM Irina Ryapolova <irina.ryapol...@syntacore.com> wrote: > > From: Vadim Shakirov <vadim.shaki...@syntacore.com> > > In the AIA specification in the paragraph "Virtual interrupts for VS level" > it is indicated for interrupts 13-63: if the bit in hideleg is enabled, > then the corresponding vsip and vsie bits are aliases to sip and sie
@Atish Patra in case you know something I don't > > Signed-off-by: Vadim Shakirov <vadim.shaki...@syntacore.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 0c21145eaf..51b1099e10 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1136,7 +1136,7 @@ static RISCVException write_stimecmph(CPURISCVState > *env, int csrno, > static const uint64_t delegable_ints = > S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; > static const uint64_t vs_delegable_ints = > - (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; > + VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > static const uint64_t all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | > HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ > -- > 2.25.1 > >
