On Thu Feb 22, 2024 at 9:33 PM AEST, BALATON Zoltan wrote:
> Most exceptions are raised with nip pointing to the faulting
> instruction but the sc instruction generating a syscall exception
> leaves nip pointing to next instruction. Fix gen_sc to not use
> gen_exception_err() which sets nip back but correctly set nip to
> pc_next so we don't have to patch this in the exception handlers.
>
> Signed-off-by: BALATON Zoltan <bala...@eik.bme.hu>
> Reviewed-by: Nicholas Piggin <npig...@gmail.com>
Mixed feelings about this one still but I suppose I will add it
now you have the tracing corrected. Although one more thing:
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 049f636927..6a43eda3b9 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -4535,15 +4535,17 @@ static void gen_hrfid(DisasContext *ctx)
> #endif
> static void gen_sc(DisasContext *ctx)
> {
> - uint32_t lev;
> -
> /*
> * LEV is a 7-bit field, but the top 6 bits are treated as a reserved
> * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
> * for Ultravisor which TCG does not support, so just ignore the top 6.
> */
> - lev = (ctx->opcode >> 5) & 0x1;
> - gen_exception_err(ctx, POWERPC_SYSCALL, lev);
> + uint32_t lev = (ctx->opcode >> 5) & 0x1;
> +
> + gen_update_nip(ctx, ctx->base.pc_next);
> + gen_helper_raise_exception_err(tcg_env,
> tcg_constant_i32(POWERPC_SYSCALL),
> + tcg_constant_i32(lev));
> + ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> #if defined(TARGET_PPC64)
Can you share this code with gen_exception_err, by making
gen_exception_err_nip that takes the nip?
Thanks,
Nick
