Hi JeeHeng, > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index d7cb0f1e49b4..4b5c551fe7f0 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -7582,6 +7582,27 @@ static void x86_cpu_realizefn(DeviceState *dev, > > Error **errp) > > > > #ifndef CONFIG_USER_ONLY > > MachineState *ms = MACHINE(qdev_get_machine()); > > + > > + if (ms->smp_cache.l1d != CPU_TOPO_LEVEL_INVALID) { > > + env->cache_info_cpuid4.l1d_cache->share_level = ms->smp_cache.l1d; > > + env->cache_info_amd.l1d_cache->share_level = ms->smp_cache.l1d; > > + } > > + > > + if (ms->smp_cache.l1i != CPU_TOPO_LEVEL_INVALID) { > > + env->cache_info_cpuid4.l1i_cache->share_level = ms->smp_cache.l1i; > > + env->cache_info_amd.l1i_cache->share_level = ms->smp_cache.l1i; > > + } > > + > > + if (ms->smp_cache.l2 != CPU_TOPO_LEVEL_INVALID) { > > + env->cache_info_cpuid4.l2_cache->share_level = ms->smp_cache.l2; > > + env->cache_info_amd.l2_cache->share_level = ms->smp_cache.l2; > > + } > > + > > + if (ms->smp_cache.l3 != CPU_TOPO_LEVEL_INVALID) { > > + env->cache_info_cpuid4.l3_cache->share_level = ms->smp_cache.l3; > > + env->cache_info_amd.l3_cache->share_level = ms->smp_cache.l3; > > + } > > + > > I think this block of code can be further optimized. Maybe we can create > a function called updateCacheShareLevel() that takes a cache pointer and > a share level as arguments. This function encapsulates the common > pattern of updating cache share levels for different caches. You can define > it like this: > void updateCacheShareLevel(XxxCacheInfo *cache, int shareLevel) { > if (shareLevel != CPU_TOPO_LEVEL_INVALID) { > cache->share_level = shareLevel; > } > } >
Good idea! Will try this way. Thanks, Zhao