"Ho-Ren (Jack) Chuang" <horenchu...@bytedance.com> writes: > On Mon, Mar 4, 2024 at 10:36 PM Huang, Ying <ying.hu...@intel.com> wrote: >> >> "Ho-Ren (Jack) Chuang" <horenchu...@bytedance.com> writes: >> >> > On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying <ying.hu...@intel.com> wrote: >> >> >> >> "Ho-Ren (Jack) Chuang" <horenchu...@bytedance.com> writes: >> >> >> >> > The memory tiering component in the kernel is functionally useless for >> >> > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the >> >> > nodes >> >> > are lumped together in the DRAM tier. >> >> > https://lore.kernel.org/linux-mm/ph0pr08mb7955e9f08ccb64f23963b5c3a8...@ph0pr08mb7955.namprd08.prod.outlook.com/T/ >> >> >> >> I think that it's unfair to call it "useless". Yes, it doesn't work if >> >> the CXL memory device are not enumerate via drivers/dax/kmem.c. So, >> >> please be specific about in which cases it doesn't work instead of too >> >> general "useless". >> >> >> > >> > Thank you and I didn't mean anything specific. I simply reused phrases >> > we discussed >> > earlier in the previous patchset. I will change them to the following in >> > v2: >> > "At boot time, current memory tiering assigns all detected memory nodes >> > to the same DRAM tier. This results in CPUless memory/non-DRAM devices, >> > such as CXL1.1 type3 memory, being unable to be assigned to the >> > correct memory tier, >> > leading to the inability to migrate pages between different types of >> > memory." >> > >> > Please see if this looks more specific. >> >> I don't think that the description above is accurate. In fact, there >> are 2 ways to enumerate the memory device, >> >> 1. Mark it as reserved memory (E820_TYPE_SOFT_RESERVED, etc.) in E820 >> table or something similar. >> >> 2. Mark it as normal memory (E820_TYPE_RAM) in E820 table or something >> similar >> >> For 1, the memory device (including CXL memory) is onlined via >> drivers/dax/kmem.c, so will be put in proper memory tiers. For 2, the >> memory device is indistinguishable with normal DRAM with current >> implementation. And this is what this patch is working on. >> >> Right? > > Good point! How about this?: > " > When a memory device, such as CXL1.1 type3 memory, is emulated as > normal memory (E820_TYPE_RAM), the memory device is indistinguishable > from normal DRAM in terms of memory tiering with the current implementation. > The current memory tiering assigns all detected normal memory nodes > to the same DRAM tier. This results in normal memory devices with > different attributions being unable to be assigned to the correct memory tier, > leading to the inability to migrate pages between different types of memory. > "
Looks good me! Thanks! -- Best Regards, Huang, Ying
