In current implementation, the gdbstub allows reading vector registers only if V extension is supported. However, all vector extensions and vector crypto extensions have the vector registers and they all depend on Zve32x. The gdbstub should check for Zve32x instead.
Signed-off-by: Jason Chien <jason.ch...@sifive.com> Reviewed-by: Frank Chang <frank.ch...@sifive.com> Reviewed-by: Max Chou <max.c...@sifive.com> --- target/riscv/gdbstub.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ca9b71f7bb..f30de083e9 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -323,7 +323,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, 32, "riscv-32bit-fpu.xml", 0); } - if (env->misa_ext & RVV) { + if (cpu->cfg.ext_zve32x) { int base_reg = cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, -- 2.43.2