On Tue Mar 12, 2024 at 7:34 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 3/12/24 00:21, Nicholas Piggin wrote:
> > From: Benjamin Gray <bg...@linux.ibm.com>
> >
> > Add POWER10 pa-features entry.
> >
> > Notably DEXCR and and [P]HASHST/[P]HASHCHK instruction support is
>
> s/and and/and
>
> > advertised. Each DEXCR aspect is allocated a bit in the device tree,
> > using the 68--71 byte range (inclusive). The functionality of the
> > [P]HASHST/[P]HASHCHK instructions is separately declared in byte 72,
> > bit 0 (BE).
> >
> > Signed-off-by: Benjamin Gray <bg...@linux.ibm.com>
> > [npiggin: reword title and changelog, adjust a few bits]
> > Signed-off-by: Nicholas Piggin <npig...@gmail.com>
> > ---
> > hw/ppc/spapr.c | 34 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 34 insertions(+)
> >
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index 247f920f07..128bfe11a8 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -265,6 +265,36 @@ static void spapr_dt_pa_features(SpaprMachineState
> > *spapr,
> > /* 60: NM atomic, 62: RNG */
> > 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> > };
> > + /* 3.1 removes SAO, HTM support */
> > + uint8_t pa_features_31[] = { 74, 0,
> > + /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110
> > */
> > + /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */
> > + 0xf6, 0x1f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */
> > + /* 6: DS207 */
> > + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
> > + /* 16: Vector */
> > + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
> > + /* 18: Vec. Scalar, 20: Vec. XOR */
> > + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
> > + /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
> > + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
> > + /* 32: LE atomic, 34: EBB + ext EBB */
> > + 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
> > + /* 40: Radix MMU */
> > + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */
> > + /* 42: PM, 44: PC RA, 46: SC vec'd */
> > + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
> > + /* 48: SIMD, 50: QP BFP, 52: String */
> > + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
> > + /* 54: DecFP, 56: DecI, 58: SHA */
> > + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
> > + /* 60: NM atomic, 62: RNG */
> > + 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
> > + /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */
> > + 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */
> > + /* 72: [P]HASHCHK */
>
> Do we want to mention [P]HASHST as well in comment above ?
Sure. I'll do a quick respin.
Thanks,
Nick
>
> > + 0x80, 0x00, /* 72 - 73 */
> > + };
> > uint8_t *pa_features = NULL;
> > size_t pa_size;
> >
>
> In future, we may want to have helpers returning pointer to the
> pa_features array and corresponding size conditionally based on the
> required ISA support needed, instead of having local arrays bloat this
> routine.
>
> For now, with cosmetic fixes,
>
> Reviewed-by: Harsh Prateek Bora <hars...@linux.ibm.com>
>
> > @@ -280,6 +310,10 @@ static void spapr_dt_pa_features(SpaprMachineState
> > *spapr,
> > pa_features = pa_features_300;
> > pa_size = sizeof(pa_features_300);
> > }
> > + if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_10, 0,
> > cpu->compat_pvr)) {
> > + pa_features = pa_features_31;
> > + pa_size = sizeof(pa_features_31);
> > + }
> > if (!pa_features) {
> > return;
> > }
