On Thu, Mar 14, 2024 at 05:05:10PM +0530, Himanshu Chauhan wrote: > Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable > the sdtrig extension and disable the debug property for these CPUs.
The commit message needs to be updated to remove the 'and disable the debug property'. > > Signed-off-by: Himanshu Chauhan <hchau...@ventanamicro.com> > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 66c91fffd6..3c7ad1c903 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -569,6 +569,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) > cpu->cfg.cbom_blocksize = 64; > cpu->cfg.cboz_blocksize = 64; > cpu->cfg.ext_zicboz = true; > + cpu->cfg.ext_sdtrig = true; > cpu->cfg.ext_smaia = true; > cpu->cfg.ext_ssaia = true; > cpu->cfg.ext_sscofpmf = true; > -- > 2.34.1 > Thanks, drew
