On Fri, Mar 29, 2024 at 5:48 AM Philippe Mathieu-Daudé
<phi...@linaro.org> wrote:
>
> Hi Max,
>
> On 29/3/24 07:31, Max Filippov wrote:
> > - target_ipc_perm::mode and target_ipc_perm::__seq fields are 32-bit wide
> > on xtensa and thus need to use tswap32
> > - target_msqid_ds::msg_*time field pairs are reversed on big-endian
> > xtensa
>
> Please split in 2 distinct patches.
Ok.
> > struct target_msqid_ds
> > {
> > struct target_ipc_perm msg_perm;
> > +#if defined(TARGET_XTENSA) && TARGET_BIG_ENDIAN
>
> Why restrict to only Xtensa here?
I have detected and tested it on xtensa.
I see other architectures (mips, parisc, ppc, sparc) that may need
that, but AFAICS it's not that it's applicable for all big endians.
> > + abi_ulong __unused1;
> > + abi_ulong msg_stime;
> > + abi_ulong __unused2;
> > + abi_ulong msg_rtime;
> > + abi_ulong __unused3;
> > + abi_ulong msg_ctime;
> > +#else
--
Thanks.
-- Max
