Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI or CPU_INTERRUPT_VINMI, both CPSR_I and ISR_IS must be set. With CPU_INTERRUPT_VFNMI, both CPSR_F and ISR_FS must be set.
Signed-off-by: Jinjie Ruan <ruanjin...@huawei.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> --- v9: - CPU_INTERRUPT_VNMI -> CPU_INTERRUPT_VINMI. - Handle CPSR_F and ISR_FS according to CPU_INTERRUPT_VFNMI instead of CPU_INTERRUPT_VFIQ and HCRX_EL2.VFNMI. - Update the commit message. v7: - env->cp15.hcrx_el2 -> arm_hcrx_el2_eff(). - Add Reviewed-by. v6: - Verify that HCR_EL2.VF is set before checking VFNMI. v4; - Also handle VNMI. v3: - CPU_INTERRUPT_NMI do not set FIQ, so remove it. - With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set. --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08a6bc50de..97997dbd08 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1398,6 +1398,8 @@ void pmu_init(ARMCPU *cpu); #define CPSR_N (1U << 31) #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F) +#define ISR_FS (1U << 9) +#define ISR_IS (1U << 10) #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 077c9a6923..b57114d35d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2021,16 +2021,29 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { ret |= CPSR_I; } + if (cs->interrupt_request & CPU_INTERRUPT_VINMI) { + ret |= ISR_IS; + ret |= CPSR_I; + } } else { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { ret |= CPSR_I; } + + if (cs->interrupt_request & CPU_INTERRUPT_NMI) { + ret |= ISR_IS; + ret |= CPSR_I; + } } if (hcr_el2 & HCR_FMO) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { ret |= CPSR_F; } + if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) { + ret |= ISR_FS; + ret |= CPSR_F; + } } else { if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { ret |= CPSR_F; -- 2.34.1