On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan <ruanjin...@huawei.com> wrote:
>
> This patch set implements FEAT_NMI and FEAT_GICv3_NMI for ARMv8. These
> introduce support for a new category of interrupts in the architecture
> which we can use to provide NMI like functionality.
Looking through the Arm ARM pseudocode at places where it
handles NMI related features and bits, I noticed one corner
case we don't handle in this patchseries: illegal exception return.
In the pseudocode, AArch64.ExceptionReturn() calls
SetPSTATEFromPSR(), which treats PSTATE.ALLINT as one of the
bits which are reinstated from SPSR to PSTATE regardless of
whether this is an illegal exception return or not. For
QEMU that means we want to handle it the same way we do
PSTATE_DAIF and PSTATE_NZCV in the illegal_return exit path of
the exception_return helper:
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -904,8 +904,8 @@ illegal_return:
*/
env->pstate |= PSTATE_IL;
env->pc = new_pc;
- spsr &= PSTATE_NZCV | PSTATE_DAIF;
- spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
+ spsr &= PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLINT;
+ spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF | PSTATE_ALLINT);
pstate_write(env, spsr);
if (!arm_singlestep_active(env)) {
env->pstate &= ~PSTATE_SS;
(I haven't thought about whether this fits particularly into
any existing patch or should be a patch of its own.)
thanks
-- PMM
