Hi Paolo,
I just did some tests,
> + [0x98] = X86_OP_ENTRY1(CBW, 0,v), /* rAX */
> + [0x99] = X86_OP_ENTRY3(CWD, 2,v, 0,v, None, None), /* rDX, rAX */
> + [0x9A] = X86_OP_ENTRYrr(CALLF, I_unsigned,p, I_unsigned,w, chk(i64)),
X86_TYPE_I_unsigned is defined in patch 11, so the related changes
should be move into this patch to avoid compiling failures:
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -1642,6 +1642,11 @@ static bool decode_op(DisasContext *s, CPUX86State *env,
X86DecodedInsn *decode,
decode->immediate = op->imm = insn_get_signed(env, s, op->ot);
break;
+ case X86_TYPE_I_unsigned: /* Immediate */
+ op->unit = X86_OP_IMM;
+ decode->immediate = op->imm = insn_get(env, s, op->ot);
+ break;
+
case X86_TYPE_L: /* The upper 4 bits of the immediate select a 128-bit
register */
op->n = insn_get(env, s, op->ot) >> 4;
break;
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index ca99a620ce94..790ad5e1d006 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -48,6 +48,7 @@ typedef enum X86OpType {
/* Custom */
X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */
+ X86_TYPE_I_unsigned, /* Immediate, zero-extended */
X86_TYPE_2op, /* 2-operand RMW instruction */
X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
-Zhao
