The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com> --- target/riscv/helper.h | 8 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 51 +++++++++++++++- target/riscv/xtheadvector_helper.c | 58 +++++++++++++++++++ 3 files changed, 114 insertions(+), 3 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5771a4fa8a..886655899e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -2189,3 +2189,11 @@ DEF_HELPER_6(th_vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(th_vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(th_vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(th_vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_5(th_vfclass_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(th_vfclass_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(th_vfclass_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(th_vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc index 1e773c673e..8e928febb7 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -2143,15 +2143,60 @@ GEN_OPFVF_TRANS_TH(th_vmfgt_vf, opfvf_cmp_check_th) GEN_OPFVF_TRANS_TH(th_vmfge_vf, opfvf_cmp_check_th) GEN_OPFVF_TRANS_TH(th_vmford_vf, opfvf_cmp_check_th) +/* Vector Floating-Point Classify Instruction */ +GEN_OPFV_TRANS_TH(th_vfclass_v, opfv_check_th) + +/* Vector Floating-Point Merge Instruction */ +GEN_OPFVF_TRANS_TH(th_vfmerge_vfm, opfvf_check_th) + +/* Besides of check function, th_vfmv_v_f just reuse the helper_th_vmv_v_x */ +static bool trans_th_vfmv_v_f(DisasContext *s, arg_th_vfmv_v_f *a) +{ + if (require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_reg(s, a->rd, false) && + (s->sew != 0)) { + + TCGv_i64 t1; + + if (s->vl_eq_vlmax) { + t1 = tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), t1); + } else { + TCGv_ptr dest; + TCGv_i32 desc; + uint32_t data = FIELD_DP32(0, VDATA_TH, LMUL, s->lmul); + static gen_helper_vmv_vx_th * const fns[3] = { + gen_helper_th_vmv_v_x_h, + gen_helper_th_vmv_v_x_w, + gen_helper_th_vmv_v_x_d, + }; + + t1 = tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + + dest = tcg_temp_new_ptr(); + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb, + s->cfg_ptr->vlenb, data)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); + fns[s->sew - 1](dest, t1, tcg_env, desc); + } + finalize_rvv_inst(s); + return true; + } + return false; +} + #define TH_TRANS_STUB(NAME) \ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { \ return require_xtheadvector(s); \ } -TH_TRANS_STUB(th_vfclass_v) -TH_TRANS_STUB(th_vfmerge_vfm) -TH_TRANS_STUB(th_vfmv_v_f) TH_TRANS_STUB(th_vfcvt_xu_f_v) TH_TRANS_STUB(th_vfcvt_x_f_v) TH_TRANS_STUB(th_vfcvt_f_xu_v) diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c index 603b34a094..e31e13dff3 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -3147,3 +3147,61 @@ GEN_TH_CMP_VV_ENV(th_vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) GEN_TH_CMP_VF(th_vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) GEN_TH_CMP_VF(th_vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) GEN_TH_CMP_VF(th_vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) + +/* Vector Floating-Point Classify Instruction */ +#define TH_OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ + OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) + +#define GEN_TH_V(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = th_maxsz(desc) / ESZ; \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vm = th_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + env->vstart = 0; \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ +} + +THCALL(TH_OPIVV1, th_vfclass_v_h, OP_UU_H, H2, H2, fclass_h) +THCALL(TH_OPIVV1, th_vfclass_v_w, OP_UU_W, H4, H4, fclass_s) +THCALL(TH_OPIVV1, th_vfclass_v_d, OP_UU_D, H8, H8, fclass_d) +GEN_TH_V(th_vfclass_v_h, 2, 2, clearh_th) +GEN_TH_V(th_vfclass_v_w, 4, 4, clearl_th) +GEN_TH_V(th_vfclass_v_d, 8, 8, clearq_th) + +/* Vector Floating-Point Merge Instruction */ +#define GEN_VFMERGE_VF_TH(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vm = th_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t esz = sizeof(ETYPE); \ + uint32_t vlmax = th_maxsz(desc) / esz; \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i = env->vstart; i < vl; i++) { \ + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ + *((ETYPE *)vd + H(i)) \ + = (!vm && !th_elem_mask(v0, mlen, i) ? s2 : s1); \ + } \ + env->vstart = 0; \ + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +} + +GEN_VFMERGE_VF_TH(th_vfmerge_vfm_h, int16_t, H2, clearh_th) +GEN_VFMERGE_VF_TH(th_vfmerge_vfm_w, int32_t, H4, clearl_th) +GEN_VFMERGE_VF_TH(th_vfmerge_vfm_d, int64_t, H8, clearq_th) -- 2.44.0