The instruction has the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.hu...@linux.alibaba.com> --- target/riscv/helper.h | 5 ++++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 29 +++++++++++++++++- target/riscv/xtheadvector_helper.c | 30 +++++++++++++++++++ 3 files changed, 63 insertions(+), 1 deletion(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 90a1ff2601..a1c85e5254 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -2306,3 +2306,8 @@ DEF_HELPER_4(th_vmfirst_m, tl, ptr, ptr, env, i32) DEF_HELPER_5(th_vmsbf_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(th_vmsif_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(th_vmsof_m, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(th_viota_m_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(th_viota_m_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(th_viota_m_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(th_viota_m_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/riscv/insn_trans/trans_xtheadvector.c.inc index d41c691c31..93f4ee4a12 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -2534,13 +2534,40 @@ GEN_M_TRANS_TH(th_vmsbf_m) GEN_M_TRANS_TH(th_vmsif_m) GEN_M_TRANS_TH(th_vmsof_m) +/* Vector Iota Instruction */ +static bool trans_th_viota_m(DisasContext *s, arg_th_viota_m *a) +{ + if (require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_reg(s, a->rd, false) && + th_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) && + (a->vm != 0 || a->rd != 0) && + s->vstart_eq_zero) { + uint32_t data = 0; + + data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA_TH, VM, a->vm); + data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul); + static gen_helper_gvec_3_ptr * const fns[4] = { + gen_helper_th_viota_m_b, gen_helper_th_viota_m_h, + gen_helper_th_viota_m_w, gen_helper_th_viota_m_d, + }; + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), tcg_env, + s->cfg_ptr->vlenb, + s->cfg_ptr->vlenb, data, fns[s->sew]); + finalize_rvv_inst(s); + return true; + } + return false; +} + #define TH_TRANS_STUB(NAME) \ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { \ return require_xtheadvector(s); \ } -TH_TRANS_STUB(th_viota_m) TH_TRANS_STUB(th_vid_v) TH_TRANS_STUB(th_vext_x_v) TH_TRANS_STUB(th_vmv_s_x) diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector_helper.c index d4f1665bf3..b0ddb3b307 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -3622,3 +3622,33 @@ void HELPER(th_vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, { vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST); } + +/* Vector Iota Instruction */ +#define GEN_TH_VIOTA_M(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint32_t mlen = th_mlen(desc); \ + uint32_t vlmax = (env_archcpu(env)->cfg.vlenb << 3) / mlen; \ + uint32_t vm = th_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t sum = 0; \ + int i; \ + \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + H(i)) = sum; \ + if (th_elem_mask(vs2, mlen, i)) { \ + sum++; \ + } \ + } \ + env->vstart = 0; \ + CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +} + +GEN_TH_VIOTA_M(th_viota_m_b, uint8_t, H1, clearb_th) +GEN_TH_VIOTA_M(th_viota_m_h, uint16_t, H2, clearh_th) +GEN_TH_VIOTA_M(th_viota_m_w, uint32_t, H4, clearl_th) +GEN_TH_VIOTA_M(th_viota_m_d, uint64_t, H8, clearq_th) -- 2.44.0