On Fri, Mar 15, 2024 at 5:02 AM Himanshu Chauhan <hchau...@ventanamicro.com> wrote: > > This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled. > The sdtrig extension may or may not be implemented in a system. Therefore, the > -cpu rv64,sdtrig=<true/false> > option can be used to dynamically turn sdtrig extension on or off. > > By default, the sdtrig extension is disabled and debug property enabled as > usual. > > Signed-off-by: Himanshu Chauhan <hchau...@ventanamicro.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ab631500ac..4231f36c1b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -175,6 +175,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > @@ -1485,6 +1486,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false), > MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), > > + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, false), > MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), > -- > 2.34.1 > >