On 2024/5/10 14:58, Fea.Wang wrote:
Based on the priv-1.13.0, add the exception codes for Software-check and
Hardware-error.
Signed-off-by: Fea.Wang <fea.w...@sifive.com>
Reviewed-by: Frank Chang <frank.ch...@sifive.com>
---
target/riscv/cpu_bits.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index f888025c59..f037f727d9 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -673,6 +673,8 @@ typedef enum RISCVException {
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
+ RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */
+ RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */
Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
Zhiwei
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
