On Fri, Mar 22, 2024 at 7:33 PM Max Chou <max.c...@sifive.com> wrote: > > When SEW is 16, we need to check whether the Zvfhmin is enabled for the > single width operator for vector floating point widen/narrow > instructions. > > The commits in this patchset fix the single width operator checking and > remove the redudant SEW checking for vector floating point widen/narrow > instructions. > > v2: > Group patchset and rebase to the riscv-to-apply.next branch(commit 385e575) > > > Thanks to those who have already reviewed: > > Daniel Henrique Barboza dbarb...@ventanamicro.com > [PATCH] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and > vfncvt.f.f.w instructions > [PATCH] target/riscv: rvv: Check single width operator for vector fp > widen instructions > [PATCH] target/riscv: rvv: Check single width operator for > vfncvt.rod.f.f.w > [PATCH] target/riscv: rvv: Remove redudant SEW checking for vector fp > narrow/widen instructions > > > Max Chou (4): > target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and > vfncvt.f.f.w instructions > target/riscv: rvv: Check single width operator for vector fp widen > instructions > target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w > target/riscv: rvv: Remove redudant SEW checking for vector fp > narrow/widen instructions
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/insn_trans/trans_rvv.c.inc | 42 ++++++++++++++++--------- > 1 file changed, 28 insertions(+), 14 deletions(-) > > -- > 2.34.1 > >
