>From the Freescale PowerPC Architecture Primer: Alternate time base APU. This APU, implemented on the e500v2, defines a 64-bit time base counter that differs from the PowerPC defined time base in that it is not writable and counts at a different, and typically much higher, frequency. The alternate time base always counts up, wrapping when the 64-bit count overflows.
This implementation of ATB uses the same frequency as the TB. The existing spr_read_atbu/l functions are unused without this patch to wire them into the SPR. RTEMS uses this SPR on the e6500, though this hasn't been tested. Signed-off-by: Nicholas Piggin <npig...@gmail.com> --- target/ppc/cpu_init.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 927721d49a..892fb6ce02 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -920,6 +920,18 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, #endif } +static void register_atb_sprs(CPUPPCState *env) +{ + spr_register(env, SPR_ATBL, "ATBL", + &spr_read_atbl, SPR_NOACCESS, + &spr_read_atbl, SPR_NOACCESS, + 0x00000000); + spr_register(env, SPR_ATBU, "ATBU", + &spr_read_atbu, SPR_NOACCESS, + &spr_read_atbu, SPR_NOACCESS, + 0x00000000); +} + /* SPR specific to PowerPC 440 implementation */ static void register_440_sprs(CPUPPCState *env) { @@ -2927,6 +2939,11 @@ static void init_proc_e500(CPUPPCState *env, int version) register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); register_usprgh_sprs(env); + if (version != fsl_e500v1) { + /* e500v1 has no support for alternate timebase */ + register_atb_sprs(env); + } + spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, -- 2.43.0