From: Clément Mathieu--Drif <clement.mathieu--d...@eviden.com> Signed-off-by: Clément Mathieu--Drif <clement.mathieu--d...@eviden.com> Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com> --- hw/i386/intel_iommu_internal.h | 3 +++ hw/i386/intel_iommu.c | 25 +++++++++++++++++++++++++ 2 files changed, 28 insertions(+)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index b6820dbca3..c0a94af820 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -327,6 +327,7 @@ typedef enum VTDFaultReason { /* Output address in the interrupt address range for scalable mode */ VTD_FR_SM_INTERRUPT_ADDR = 0x87, + VTD_FR_FS_BIT_UPDATE_FAILED = 0x91, /* SFS.10 */ VTD_FR_MAX, /* Guard */ } VTDFaultReason; @@ -547,6 +548,8 @@ typedef struct VTDRootEntry VTDRootEntry; /* First Level Paging Structure */ #define VTD_FL_PT_LEVEL 1 #define VTD_FL_PT_ENTRY_NR 512 +#define VTD_FL_PTE_A 0x20 +#define VTD_FL_PTE_D 0x40 /* Masks for First Level Paging Entry */ #define VTD_FL_RW_MASK (1ULL << 1) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1ea030bfbe..0801112e2e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1802,6 +1802,7 @@ static const bool vtd_qualified_faults[] = { [VTD_FR_PASID_TABLE_ENTRY_INV] = true, [VTD_FR_SM_INTERRUPT_ADDR] = true, [VTD_FR_FS_NON_CANONICAL] = true, + [VTD_FR_FS_BIT_UPDATE_FAILED] = true, [VTD_FR_MAX] = false, }; @@ -1927,6 +1928,20 @@ static bool vtd_iova_fl_check_canonical(IntelIOMMUState *s, uint64_t iova, ); } +static MemTxResult vtd_set_flag_in_pte(dma_addr_t base_addr, uint32_t index, + uint64_t pte, uint64_t flag) +{ + if (pte & flag) { + return MEMTX_OK; + } + pte |= flag; + pte = cpu_to_le64(pte); + return dma_memory_write(&address_space_memory, + base_addr + index * sizeof(pte), + &pte, sizeof(pte), + MEMTXATTRS_UNSPECIFIED); +} + /* * Given the @iova, get relevant @flptep. @flpte_level will be the last level * of the translation, can be used for deciding the size of large page. @@ -1972,7 +1987,17 @@ static int vtd_iova_to_flpte(IntelIOMMUState *s, VTDContextEntry *ce, return -VTD_FR_WRITE; } + if (vtd_set_flag_in_pte(addr, offset, flpte, VTD_FL_PTE_A) + != MEMTX_OK) { + return -VTD_FR_FS_BIT_UPDATE_FAILED; + } + if (vtd_is_last_flpte(flpte, level)) { + if (is_write && + (vtd_set_flag_in_pte(addr, offset, flpte, VTD_FL_PTE_D) != + MEMTX_OK)) { + return -VTD_FR_FS_BIT_UPDATE_FAILED; + } *flptep = flpte; *flpte_level = level; return 0; -- 2.34.1