On 5/25/24 21:37, LIU Zhiwei wrote:
On 2024/5/24 19:44, Daniel Henrique Barboza wrote:
Hi Zhiwei!
On 5/23/24 09:40, LIU Zhiwei wrote:
Zabha adds support AMO operations for byte and half word. If zacas has been
implemented,
zabha also adds support amocas.b and amocas.h.
More details is on the specification here:
https://github.com/riscv/riscv-zabha
The implemenation of zabha follows the way of AMOs and zacas.
This patch set is based on these two patch set:
1. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00207.html
2. https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
These 2 series doesn't seem to apply on top of each other, doesn't matter which
order I try. Applying zimop/zcmop first, then zama16b:
$ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\ -\ LIU\ Zhiwei\
\<zhiwei_...@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
Applying: target/riscv: Support Zama16b extension
error: patch failed: target/riscv/cpu.c:1464
error: target/riscv/cpu.c: patch does not apply
Patch failed at 0001 target/riscv: Support Zama16b extension
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Applying zama16b first, then zimop/zcmop:
$ git am \[PATCH\ 1_1\]\ target_riscv\:\ Support\ Zama16b\ extension\ -\ LIU\ Zhiwei\
\<zhiwei_...@linux.alibaba.com\>\ -\ 2024-05-22\ 0613.eml
Applying: target/riscv: Support Zama16b extension
$
$ git am \[PATCH\ 1_4\]\ target_riscv\:\ Add\ zimop\ extension\ -\ LIU\ Zhiwei\
\<zhiwei_...@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml \[PATCH\ 2_4\]\
disas_riscv\:\ Support\ zimop\ disassemble\ -\ LIU\ Zhiwei\
\<zhiwei_...@linux.alibaba.com\>\ -\ 2024-05-22\ 0329.eml
Applying: target/riscv: Add zimop extension
error: patch failed: target/riscv/cpu.c:1463
error: target/riscv/cpu.c: patch does not apply
Patch failed at 0001 target/riscv: Add zimop extension
If the series are dependent on each other perhaps it's easier to send everything
in a single 11 patches series.
They don't have dependency on each other. But if we both rebase them to the
master branch, they
couldn't be merged at the time, as them both modify cpu.h and cpu.c in the same
place.
I will send them as a whole patch set(RVA23 patch set) after I fix other issues
on implementing the RVA23 profile.
Be aware that we have some RVA23 extensions that are implemented in the ML
but not merged no master yet. E.g. sstvala ended up being implemented after some
changes I did w.r.t tval and EBREAK. These patches are on riscv-to-apply.next.
Also, I took another look at RVA23 mandatory exts and what we have. I think
we're
not that far off after these extensions you're adding. What we really seems to
be
missing is supm and ssnpm.
Thanks,
Daniel
Thanks,
Zhiwei
Thanks,
Daniel
LIU Zhiwei (6):
target/riscv: Move gen_amo before implement Zabha
target/riscv: Add AMO instructions for Zabha
target/riscv: Move gen_cmpxchg before adding amocas.[b|h]
target/riscv: Add amocas.[b|h] for Zabha
target/riscv: Enable zabha for max cpu
disas/riscv: Support zabha disassemble
disas/riscv.c | 60 ++++++++
target/riscv/cpu.c | 2 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 22 +++
target/riscv/insn_trans/trans_rva.c.inc | 21 ---
target/riscv/insn_trans/trans_rvzabha.c.inc | 145 ++++++++++++++++++++
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 --
target/riscv/translate.c | 36 +++++
8 files changed, 266 insertions(+), 34 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
