For test_arch64.s and test_arm.s, use '.inst' so that the risu
control insns are marked as instructions for disassembly.
For test_i386.S, split the data to be loaded into the data section;
fix an error aligning the data: 16 not 2**16.
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
Makefile | 19 ++++++++++---------
test.ld | 12 ++++++++++++
test_aarch64.s | 4 ++--
test_arm.s | 16 +++++++++++-----
test_i386.S | 4 +++-
5 files changed, 38 insertions(+), 17 deletions(-)
create mode 100644 test.ld
diff --git a/Makefile b/Makefile
index ad7f879..2bd08aa 100644
--- a/Makefile
+++ b/Makefile
@@ -22,7 +22,8 @@ ALL_CFLAGS = -Wall -D_GNU_SOURCE -DARCH=$(ARCH) -U$(ARCH)
$(BUILD_INC) $(CFLAGS)
PROG=risu
SRCS=risu.c comms.c risu_$(ARCH).c risu_reginfo_$(ARCH).c
HDRS=risu.h risu_reginfo_$(ARCH).h
-BINS=test_$(ARCH).bin
+BINO=test_$(ARCH).o
+BINE=test_$(ARCH).elf
# For dumping test patterns
RISU_BINS=$(wildcard *.risu.bin)
@@ -30,7 +31,7 @@ RISU_ASMS=$(patsubst %.bin,%.asm,$(RISU_BINS))
OBJS=$(SRCS:.c=.o)
-all: $(PROG) $(BINS)
+all: $(PROG) $(BINE)
dump: $(RISU_ASMS)
@@ -43,17 +44,17 @@ $(PROG): $(OBJS)
%.o: %.c $(HDRS)
$(CC) $(CPPFLAGS) $(ALL_CFLAGS) -o $@ -c $<
-%_$(ARCH).bin: %_$(ARCH).elf
- $(OBJCOPY) -O binary $< $@
+%_$(ARCH).o: %_$(ARCH).s
+ $(CC) -o $@ -c $<
-%_$(ARCH).elf: %_$(ARCH).s
- $(AS) -o $@ $<
-
-%_$(ARCH).elf: %_$(ARCH).S
+%_$(ARCH).o: %_$(ARCH).S
$(CC) $(CPPFLAGS) -o $@ -c $<
+%_$(ARCH).elf: test.ld %_$(ARCH).o
+ $(LD) -o $@ -T $^
+
clean:
- rm -f $(PROG) $(OBJS) $(BINS)
+ rm -f $(PROG) $(OBJS) $(BINO) $(BINE)
distclean: clean
rm -f config.h Makefile.in
diff --git a/test.ld b/test.ld
new file mode 100644
index 0000000..eb0a76a
--- /dev/null
+++ b/test.ld
@@ -0,0 +1,12 @@
+ENTRY(start)
+
+PHDRS {
+ text PT_LOAD FILEHDR PHDRS;
+}
+
+SECTIONS {
+ . = SIZEOF_HEADERS;
+ PROVIDE(start = .);
+ .text : { *(.text) } :text
+ .data : { *(.data) } :text
+}
diff --git a/test_aarch64.s b/test_aarch64.s
index f75d588..88902c6 100644
--- a/test_aarch64.s
+++ b/test_aarch64.s
@@ -80,6 +80,6 @@ fmov d31, #31.0
/* do compare.
* The manual says instr with bits (28,27) == 0 0 are UNALLOCATED
*/
-.int 0x00005af0
+.inst 0x00005af0
/* exit test */
-.int 0x00005af1
+.inst 0x00005af1
diff --git a/test_arm.s b/test_arm.s
index 49552f2..62582e7 100644
--- a/test_arm.s
+++ b/test_arm.s
@@ -9,20 +9,26 @@
* Peter Maydell (Linaro) - initial implementation
*******************************************************************************/
+.text
+
/* magic instruction to force ARM mode whether we were in ARM or Thumb before
*/
-.int 0xe0004778
+.inst 0xe0004778
+
/* Initialise the gp regs */
add r0, pc, #4
ldmia r0, {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r14}
-b next
+b 1f
+
.int 0,1,2,3,4,5,6,7,8,9,10,11,12,14
-next:
+
+1:
msr CPSR_fs, #0
+
/* do compare.
* The space 0xE7F___F_ is guaranteed to always UNDEF
* and not to be allocated for insns in future architecture
* revisions.
*/
-.int 0xe7fe5af0
+.inst 0xe7fe5af0
/* exit test */
-.int 0xe7fe5af1
+.inst 0xe7fe5af1
diff --git a/test_i386.S b/test_i386.S
index 05344d7..2e2b090 100644
--- a/test_i386.S
+++ b/test_i386.S
@@ -13,6 +13,7 @@
/* Initialise the registers to avoid spurious mismatches */
+.text
#ifdef __x86_64__
#define BASE %rax
lea 2f(%rip), BASE
@@ -71,7 +72,8 @@
/* exit test */
ud1 %ecx, %eax
- .p2align 16
+.data
+ .balign 16
2:
.set i, 0
.rept 256
--
2.34.1
