From: Paolo Bonzini <pbonz...@redhat.com> Intel SDM 18.3.1.4 "If an occurrence of the MOV or POP instruction loads the SS register executes with EFLAGS.TF = 1, no single-step debug exception occurs following the MOV or POP instruction."
Cc: qemu-sta...@nongnu.org Signed-off-by: Paolo Bonzini <pbonz...@redhat.com> (cherry picked from commit f0f0136abba688a6516647a79cc91e03fad6d5d7) Signed-off-by: Michael Tokarev <m...@tls.msk.ru> (Mjt: context fixup for v8.1.0-1189-gad75a51e84af "tcg: Rename cpu_env to tcg_env") diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index f8578ad1ea..0d47b61603 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2823,7 +2823,7 @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr) if (recheck_tf) { gen_helper_rechecking_single_step(cpu_env); tcg_gen_exit_tb(NULL, 0); - } else if (s->flags & HF_TF_MASK) { + } else if ((s->flags & HF_TF_MASK) && !inhibit) { gen_helper_single_step(cpu_env); } else if (jr && /* give irqs a chance to happen */ -- 2.39.2