Fea, Please try to also add all RISC-V QEMU maintainers and reviewers when sending patches. It will get your patches reviewed and queued faster. Otherwise the maintainers can miss you your series due to high ML traffic.
You can fetch who you want to CC using the get_maintainer.pl script with the patch files or any source file in particular, e.g.: $ ./scripts/get_maintainer.pl -f target/riscv/cpu.c Palmer Dabbelt <pal...@dabbelt.com> (supporter:RISC-V TCG CPUs) Alistair Francis <alistair.fran...@wdc.com> (supporter:RISC-V TCG CPUs) Bin Meng <bmeng...@gmail.com> (supporter:RISC-V TCG CPUs) Weiwei Li <liwei1...@gmail.com> (reviewer:RISC-V TCG CPUs) Daniel Henrique Barboza <dbarb...@ventanamicro.com> (reviewer:RISC-V TCG CPUs) Liu Zhiwei <zhiwei_...@linux.alibaba.com> (reviewer:RISC-V TCG CPUs) qemu-ri...@nongnu.org (open list:RISC-V TCG CPUs) qemu-devel@nongnu.org (open list:All patches CC here) I added the extra folk in the CC for this reply so don't worry about it. Alistair, please queue this series. It's already fully acked and I would like to add some bits on top of the priv_spec 1.13 support. Thanks, Daniel On 5/15/24 05:05, Fea.Wang wrote:
Based on the change log for the RISC-V privilege 1.13 spec, add the support for ss1p13. Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72 Lists what to do without clarification or document format. * Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip, implementation ignored) * Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored) * Defined the misa.V field to reflect that the V extension has been implemented.(Skip, existed) * Defined the RV32-only medelegh and hedelegh CSRs.(Done in these patches) * Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension..(Skip, implementation ignored) * Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed) * Defined hardware error and software check exception codes.(Done in these patches) * Specified synchronization requirements when changing the PBMTE fields in menvcfg and henvcfg.(Skip, implementation ignored) * Incorporated Svade and Svadu extension specifications.(Skip, existed) Fea.Wang (4): target/riscv: Support the version for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Reserve exception codes for sw-check and hw-err Jim Shu (1): target/riscv: Reuse the conversion function of priv_spec target/riscv/cpu.c | 8 ++++++-- target/riscv/cpu.h | 5 ++++- target/riscv/cpu_bits.h | 5 +++++ target/riscv/cpu_cfg.h | 1 + target/riscv/csr.c | 39 ++++++++++++++++++++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 17 ++++++++--------- 6 files changed, 63 insertions(+), 12 deletions(-)
