On Sat, 25 May 2024 at 00:23, Richard Henderson <richard.hender...@linaro.org> wrote: > > This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2, > but are introduced with ARMv7 and ARMv7MP respectively. > For clarity, do not use NOP for PLD. > > Note that there is no PLDW (literal) -- bit 5 of the first word > is not decoded, and is PLD (literal). Confirmed on neoverse-n1 > host which does *not* trap on the (0) bit in the decode.
Handling of "(0)" and "(1)" bits in decode is CONSTRAINED UNPREDICTABLE (see Arm ARM DDI0487K.a F1.7.2): implementations might: * UNDEF * NOP * ignore the bit and execute the insn * set any destination registers to UNKNOWN values Usually (but not always) in QEMU we opt to UNDEF. If I'm reading the decode lines correctly here in this case we're opting to ignore the bit because we have both: + PLD 1111 1000 -001 1111 1111 ------------ # (literal) + PLD 1111 1000 -011 1111 1111 ------------ # (literal) And this isn't a change in this commit because the NOP lines we used to have also meant we ignored the bit. With a tweaked commit message Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
