On 5/28/24 07:07, Peter Maydell wrote:
Hi; most of this is the first half of the A64 simd decodetree
conversion; the rest is a mix of fixes from the last couple of weeks.
v2 uses patches from the v2 decodetree series to avoid a few
regressions in some A32 insns.
(Richard: I'm still planning to review the second half of the
v2 decodetree series; I just wanted to get the respin of this
pullreq out today...)
thanks
-- PMM
The following changes since commit ad10b4badc1dd5b28305f9b9f1168cf0aa3ae946:
Merge tag 'pull-error-2024-05-27' ofhttps://repo.or.cz/qemu/armbru into
staging (2024-05-27 06:40:42 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20240528
for you to fetch changes up to f240df3c31b40e4cf1af1f156a88efc1a1df406c:
target/arm: Convert disas_simd_3same_logic to decodetree (2024-05-28
14:29:01 +0100)
----------------------------------------------------------------
target-arm queue:
* xlnx_dpdma: fix descriptor endianness bug
* hvf: arm: Fix encodings for ID_AA64PFR1_EL1 and debug System registers
* hw/arm/npcm7xx: remove setting of mp-affinity
* hw/char: Correct STM32L4x5 usart register CR2 field ADD_0 size
* hw/intc/arm_gic: Fix handling of NS view of GICC_APR<n>
* hw/input/tsc2005: Fix -Wchar-subscripts warning in tsc2005_txrx()
* hw: arm: Remove use of tabs in some source files
* docs/system: Remove ADC from raspi documentation
* target/arm: Start of the conversion of A64 SIMD to decodetree
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as
appropriate.
r~
