From: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2304
Reported-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiew...@linaro.org>
Message-id: 20240526204551.553282-1-richard.hender...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
target/arm/cpu64.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c15d086049f..862d2b92fa4 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -109,7 +109,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
* No explicit bits enabled, and no implicit bits from sve-max-vq.
*/
if (!cpu_isar_feature(aa64_sve, cpu)) {
- /* SVE is disabled and so are all vector lengths. Good. */
+ /*
+ * SVE is disabled and so are all vector lengths. Good.
+ * Disable all SVE extensions as well.
+ */
+ cpu->isar.id_aa64zfr0 = 0;
return;
}
--
2.34.1
