From: Frank Chang <frank.ch...@sifive.com> Currently, the implied extensions are enabled and checked in riscv_cpu_validate_set_extensions(). However, the order of enabling the implied extensions must follow a strict sequence, which is error-prone.
This patchset introduce extension implied rule helpers to enable the implied extensions. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc., removing the need to check the implied rules of Zvksg before Zvks. The idea [1] and the implied rules [2] are referenced from LLVM. [1] https://github.com/llvm/llvm-project/blob/main/llvm/lib/TargetParser/RISCVISAInfo.cpp#L875 [2] https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVFeatures.td Frank Chang (6): target/riscv: Introduce extension implied rules definition target/riscv: Introduce extension implied rule helpers target/riscv: Add MISA implied rules target/riscv: Add standard extension implied rules target/riscv: Add Zc extension implied rule target/riscv: Remove extension auto-update check statements target/riscv/cpu.c | 396 +++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 17 ++ target/riscv/tcg/tcg-cpu.c | 233 +++++++++++----------- 3 files changed, 531 insertions(+), 115 deletions(-) -- 2.43.2
