Re: [PATCH v2 08/37] target/sparc: Use gvec for VIS1 parallel add/sub

[Philippe Mathieu-Daudé]

On 26/5/24 21:42, Richard Henderson wrote:

Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
  target/sparc/translate.c | 18 ++++++++++++++----
  1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 362e88de18..8731e4f8bb 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -4664,6 +4664,20 @@ static bool do_dfd(DisasContext *dc, arg_r_r_r *a,

TRANS(FMUL8x16, VIS1, do_dfd, a, gen_helper_fmul8x16) +static bool do_gvec_ddd(DisasContext *dc, arg_r_r_r *a, MemOp vece,

+                        void (*func)(unsigned, uint32_t, uint32_t,
+                                     uint32_t, uint32_t, uint32_t))
+{

I missed the FPU check I guess:

    if (gen_trap_ifnofpu(dc)) {
        return true;
    }

+    func(vece, gen_offset_fpr_D(a->rd), gen_offset_fpr_D(a->rs1),
+         gen_offset_fpr_D(a->rs2), 8, 8);
+    return advance_pc(dc);
+}