There is no dependency on Smcsrind, only Sscsrind. On Tue, Jun 4, 2024 at 12:29 AM Jason Chien <jason.ch...@sifive.com> wrote:
> Smctr depends on the Smcsrind extension, Ssctr depends on the Sscsrind > extension, and both Smctr and Ssctr depend upon implementation of S-mode. > There should be a dependency check in riscv_cpu_validate_set_extensions(). > > Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道: > > This series enables Control Transfer Records extension support on riscv > > platform. This extension is similar to Arch LBR in x86 and BRBE in ARM. > > The Extension has been stable and the latest release can be found here > [0] > > > > CTR extension depends on couple of other extensions: > > > > 1. S[m|s]csrind : The indirect CSR extension [1] which defines additional > > ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitation of > > RISC-V CSR address space. CTR access ctrsource, ctrtartget and > ctrdata > > CSRs using sscsrind extension. > > > > 2. Smstateen: The mstateen bit[54] controls the access to the CTR ext to > > S-mode. > > > > 3. Sscofpmf: Counter overflow and privilege mode filtering. [2] > > > > The series is based on Smcdeleg/Ssccfg counter delegation extension [3] > > patches. CTR itself doesn't depend on counter delegation support. This > > rebase is basically to include the Smcsrind patches. > > > > Due to the dependency of these extensions, the following extensions must > be > > enabled to use the control transfer records feature. > > > > > "smstateen=true,sscofpmf=true,smcsrind=true,sscsrind=true,smctr=true,ssctr=true" > > > > Here is the link to a quick guide [5] to setup and run a basic perf demo > on > > Linux to use CTR Ext. > > > > The Qemu patches can be found here: > > https://github.com/rajnesh-kanwal/qemu/tree/ctr_upstream > > > > The opensbi patch can be found here: > > https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream > > > > The Linux kernel patches can be found here: > > https://github.com/rajnesh-kanwal/linux/tree/ctr_upstream > > > > [0]:https://github.com/riscv/riscv-control-transfer-records/release > > [1]:https://github.com/riscv/riscv-indirect-csr-access > > [2]:https://github.com/riscvarchive/riscv-count-overflow/tree/main > > [3]:https://github.com/riscv/riscv-smcdeleg-ssccfg > > [4]: > https://lore.kernel.org/all/20240217000134.3634191-1-ati...@rivosinc.com/ > > [5]: > https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine > > > > Rajnesh Kanwal (6): > > target/riscv: Remove obsolete sfence.vm instruction > > target/riscv: Add Control Transfer Records CSR definitions. > > target/riscv: Add support for Control Transfer Records extension CSRs. > > target/riscv: Add support to record CTR entries. > > target/riscv: Add CTR sctrclr instruction. > > target/riscv: Add support to access ctrsource, ctrtarget, ctrdata > > regs. > > > > target/riscv/cpu.c | 4 + > > target/riscv/cpu.h | 14 + > > target/riscv/cpu_bits.h | 154 +++++++++ > > target/riscv/cpu_cfg.h | 2 + > > target/riscv/cpu_helper.c | 213 ++++++++++++ > > target/riscv/csr.c | 312 +++++++++++++++++- > > target/riscv/helper.h | 8 +- > > target/riscv/insn32.decode | 2 +- > > .../riscv/insn_trans/trans_privileged.c.inc | 21 +- > > target/riscv/insn_trans/trans_rvi.c.inc | 27 ++ > > target/riscv/op_helper.c | 117 ++++++- > > target/riscv/translate.c | 9 + > > 12 files changed, 870 insertions(+), 13 deletions(-) > > >
