Hi Eric,
On Mon, May 20, 2024 at 03:30:58PM +0200, Eric Auger wrote:
>
>
> On 4/29/24 05:23, Mostafa Saleh wrote:
> > QEMU doesn's support memory attributes, so FWB is NOP, this
> > might change in the future if memory attributre would be supported.
> if mem attributes get supported
> >
> > Signed-off-by: Mostafa Saleh <smost...@google.com>
> > ---
> > hw/arm/smmuv3.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> > index 88f6473d33..8a11e41144 100644
> > --- a/hw/arm/smmuv3.c
> > +++ b/hw/arm/smmuv3.c
> > @@ -287,6 +287,14 @@ static void smmuv3_init_regs(SMMUv3State *s)
> > if (FIELD_EX32(s->idr[0], IDR0, S2P)) {
> > /* XNX is a stage-2-specific feature */
> > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, XNX, 1);
> > + if (FIELD_EX32(s->idr[0], IDR0, S1P)) {
> > + /*
> > + * QEMU doesn's support memory attributes, so FWB is NOP, this
> > + * might change in the future if memory attributre would be
> if mem attributes get supported
> > + * supported.
> > + */
> > + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, FWB, 1);
> spec says:
> 0b0 Stage 2 control of memory types and attributes is
> not supported and the STE.S2FWB bit is RES 0.
My understanding it is still OK for the SMMU to advertise that although as
patch description indicates it is useless, but I thought it is similar to
XNX recently added, but I can drop it if it is not useful.
Thanks,
Mostafa
>
>
> Thanks
>
> Eric
> > + }
> > }
> > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
> > s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2);
>
