On 6/21/24 09:34, Richard Henderson wrote:
On 6/21/24 04:46, Chinmay Rath wrote:
+ tcg_gen_qemu_ld_i128(avr, EA, ctx->mem_idx, DEF_MEMOP(MO_128));
+ set_avr_full(a->rt, avr);
This needs to specify atomicity as well. This is much more important to for 16 byte
operations than smaller accesses, as this might require stop-the-world semantics depending
on the host.
According to section 1.4 Storage Atomicity, we need no more than 8-byte atomicity for
these vector operations, and then the following the alignment bits down.
So: MO_128 | MO_ATOM_IFALIGN_PAIR,
Actually, you need MO_ATOM_SUBALIGN semantics, maxing out at MO_64, which hasn't been
implemented. But since none of the rest of target/ppc has been updated to use SUBALIGN,
using IFALIGN is not a regression.
r~
