Gustavo Romero <gustavo.rom...@linaro.org> writes:

> Factor out the code used for setting the MTE TCF0 field from the prctl
> code into a convenient function. Other subsystems, like gdbstub, need to
> set this field as well, so keep it as a separate function to avoid
> duplication and ensure consistency in how this field is set across the
> board.
>
> Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
> ---
>  linux-user/aarch64/meson.build       |  2 ++
>  linux-user/aarch64/mte_user_helper.c | 34 ++++++++++++++++++++++++++++
>  linux-user/aarch64/mte_user_helper.h | 25 ++++++++++++++++++++
>  linux-user/aarch64/target_prctl.h    | 22 ++----------------
>  4 files changed, 63 insertions(+), 20 deletions(-)
>  create mode 100644 linux-user/aarch64/mte_user_helper.c
>  create mode 100644 linux-user/aarch64/mte_user_helper.h
>
> diff --git a/linux-user/aarch64/meson.build b/linux-user/aarch64/meson.build
> index 248c578d15..f75bb3cd75 100644
> --- a/linux-user/aarch64/meson.build
> +++ b/linux-user/aarch64/meson.build
> @@ -9,3 +9,5 @@ vdso_le_inc = gen_vdso.process('vdso-le.so',
>                                 extra_args: ['-r', '__kernel_rt_sigreturn'])
>  
>  linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [vdso_be_inc, 
> vdso_le_inc])
> +
> +linux_user_ss.add(when: 'TARGET_AARCH64', if_true: 
> [files('mte_user_helper.c')])
> diff --git a/linux-user/aarch64/mte_user_helper.c 
> b/linux-user/aarch64/mte_user_helper.c
> new file mode 100644
> index 0000000000..8be6deaf03
> --- /dev/null
> +++ b/linux-user/aarch64/mte_user_helper.c
> @@ -0,0 +1,34 @@
> +/*
> + * ARM MemTag convenience functions.
> + *
> + * This code is licensed under the GNU GPL v2 or later.
> + *
> + * SPDX-License-Identifier: LGPL-2.1-or-later
> + */
> +
> +#include <sys/prctl.h>

Aside from missing the osdep Phillipe pointed out including prctl.h here
is very suspect as its a system header. I assume if we need
PR_MTE_TCF_SYNC we should hoist the definition that linux-user uses into
a common header.

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro

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