Re: [PATCH v2 3/3] target/ppc : Update VSX storage access insns to use tcg_gen_qemu _ld/st_i128.

[Richard Henderson]

On 6/30/24 05:01, Chinmay Rath wrote:

@@ -2175,13 +2179,13 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv 
displ,
                       int rt, bool store, bool paired)
  {
      TCGv ea;
-    TCGv_i64 xt;
+    TCGv_i128 data;
      MemOp mop;
      int rt1, rt2;

- xt = tcg_temp_new_i64();

+    data = tcg_temp_new_i128();

- mop = DEF_MEMOP(MO_UQ);

+    mop = DEF_MEMOP(MO_128 | MO_ATOM_IFALIGN_PAIR);

gen_set_access_type(ctx, ACCESS_INT);

      ea = do_ea_calc(ctx, ra, displ);
@@ -2195,32 +2199,20 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv 
displ,
      }

if (store) {

-        get_cpu_vsr(xt, rt1, !ctx->le_mode);
-        tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
-        gen_addr_add(ctx, ea, ea, 8);
-        get_cpu_vsr(xt, rt1, ctx->le_mode);
-        tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+        get_vsr_full(data, rt1);
+        tcg_gen_qemu_st_i128(data, ea, ctx->mem_idx, mop);
          if (paired) {
              gen_addr_add(ctx, ea, ea, 8);

The increment needs updating to 16.

-            get_cpu_vsr(xt, rt2, !ctx->le_mode);
-            tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
-            gen_addr_add(ctx, ea, ea, 8);
-            get_cpu_vsr(xt, rt2, ctx->le_mode);
-            tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+            get_vsr_full(data, rt2);
+            tcg_gen_qemu_st_i128(data, ea, ctx->mem_idx, mop);
          }
      } else {
-        tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
-        set_cpu_vsr(rt1, xt, !ctx->le_mode);
-        gen_addr_add(ctx, ea, ea, 8);
-        tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
-        set_cpu_vsr(rt1, xt, ctx->le_mode);
+        tcg_gen_qemu_ld_i128(data, ea, ctx->mem_idx, mop);
+        set_vsr_full(rt1, data);
          if (paired) {
              gen_addr_add(ctx, ea, ea, 8);

Likewise.

With those fixed,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>


r~