From: Gustavo Romero <gustavo.rom...@linaro.org>
Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU
since it concerns the external debug interface for JTAG, but is
mandatory in Armv8.8 implementations, hence it is reported as supported
in the ID registers.
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20240624180915.4528-4-gustavo.rom...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
---
docs/system/arm/emulation.rst | 1 +
target/arm/tcg/cpu32.c | 6 +++---
target/arm/tcg/cpu64.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 1a06a5feb6e..3ab6e726679 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -41,6 +41,7 @@ the following architecture extensions:
- FEAT_Debugv8p1 (Debug with VHE)
- FEAT_Debugv8p2 (Debug changes for v8.2)
- FEAT_Debugv8p4 (Debug changes for v8.4)
+- FEAT_Debugv8p8 (Debug changes for v8.8)
- FEAT_DotProd (Advanced SIMD dot product instructions)
- FEAT_DoubleFault (Double Fault Extension)
- FEAT_E0PD (Preventing EL0 access to halves of address maps)
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 28a5c033bb9..20c2737f17b 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_pfr2 = t;
t = cpu->isar.id_dfr0;
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
cpu->isar.id_dfr0 = t;
@@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu)
t = 0x00008000;
t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
- t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */
+ t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 71e1bfcd4ee..fe232eb3069 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj)
cpu->isar.id_aa64zfr0 = t;
t = cpu->isar.id_aa64dfr0;
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
cpu->isar.id_aa64dfr0 = t;
--
2.34.1
