Since the downstream port is not checked, two slots can be linked to a single port. However, this can prevent the driver from detecting the device properly.
It is necessary to ensure that a downstream port is not linked more than once. Links: https://lore.kernel.org/qemu-devel/oszpr01mb6453bc61d2ff4035f18084ef8d...@oszpr01mb6453.jpnprd01.prod.outlook.com Signed-off-by: Yao Xingtao <yaoxt.f...@fujitsu.com> --- hw/pci-bridge/cxl_downstream.c | 6 ++++++ hw/pci-bridge/pcie_root_port.c | 6 ++++++ hw/pci-bridge/xio3130_downstream.c | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 742da07a01..fa33cdb36b 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -153,6 +153,12 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) goto err_bridge; } + if (pcie_find_port_by_pn(pci_get_bus(d), p->port) != NULL) { + rc = -EBUSY; + error_setg(errp, "Can't link port, error %d", rc); + goto err_msi; + } + rc = pcie_cap_init(d, CXL_DOWNSTREAM_PORT_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 09a34786bc..350137bd8c 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -89,6 +89,12 @@ static void rp_realize(PCIDevice *d, Error **errp) } } + if (pcie_find_port_by_pn(pci_get_bus(d), p->port) != NULL) { + rc = -EBUSY; + error_setg(errp, "Can't link port, error %d", rc); + goto err_int; + } + rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, p->port, errp); if (rc < 0) { diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 907d5105b0..af04d2efad 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -88,6 +88,12 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) goto err_msi; } + if (pcie_find_port_by_pn(pci_get_bus(d), p->port) != NULL) { + rc = -EBUSY; + error_setg(errp, "Can't link port, error %d", rc); + goto err_msi; + } + rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM, p->port, errp); if (rc < 0) { -- 2.37.3
