On Sat, Jul 6, 2024 at 2:54 AM Rob Bradford <rbradf...@rivosinc.com> wrote: > > From: Balaji Ravikumar <braviku...@rivosinc.com> > > Add disassembly support for these instructions from Zawrs: > > * wrs.sto > * wrs.nto > > Signed-off-by: Balaji Ravikumar <braviku...@rivosinc.com> > Signed-off-by: Rob Bradford <rbradf...@rivosinc.com>
Acked-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > disas/riscv.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/disas/riscv.c b/disas/riscv.c > index 05b663ebfe..ff0323f0dd 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -974,6 +974,8 @@ typedef enum { > rv_op_amomaxu_h = 943, > rv_op_amocas_b = 944, > rv_op_amocas_h = 945, > + rv_op_wrs_sto = 946, > + rv_op_wrs_nto = 947, > } rv_op; > > /* register names */ > @@ -2232,6 +2234,8 @@ const rv_opcode_data rvi_opcode_data[] = { > { "amomaxu.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, > { "amocas.b", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, > { "amocas.h", rv_codec_r_a, rv_fmt_aqrl_rd_rs2_rs1, NULL, 0, 0, 0 }, > + { "wrs.sto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, > + { "wrs.nto", rv_codec_none, rv_fmt_none, NULL, 0, 0, 0 }, > }; > > /* CSR names */ > @@ -4000,6 +4004,8 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa > isa) > case 0: op = rv_op_ecall; break; > case 32: op = rv_op_ebreak; break; > case 64: op = rv_op_uret; break; > + case 416: op = rv_op_wrs_nto; break; > + case 928: op = rv_op_wrs_sto; break; > } > break; > case 256: > -- > 2.45.2 > >